1. Field of the Invention
This invention relates to the field of self-aligned silicide semiconductor structures, and more specifically, to a process designed to form cobalt disilicide (CoSi.sub.2) layers for use in salicide technology.
2. Background & Related Art
In the manufacture of semiconductor devices, silicides, materials formed by the reaction of refractory metals, or near nobel metals, with silicon, are used in a variety of applications. For the past decade titanium silicide (TiSi.sub.2), has been the workhorse of the semiconductor industry due to its low contact resistance, low sheet resistance, and well-understood properties. However, as feature sizes and linewidths decrease below the 0.20 .mu.m level, the drawbacks and shortcomings of TiSi.sub.2, are becoming apparent and more critical. Thus, the effectiveness of TiSi.sub.2 is coming to an end. In the search for an effective replacement numerous alternative materials have been experimented with. One promising replacement material is cobalt disilicide (CoSi.sub.2).
One key use of silicides is in the so-called salicide process. Salicide processing is the manufacture of "self-aligned" silicide gate structures. A typical presently used process is shown in FIGS. 1A-1D. FIG. 1A begins with a self-aligned MOS transistor already formed on a silicon substrate. Such a device features a gate structure, 103, formed on an active semiconductor surface region, 101, lying between field oxide regions, 102, of a semiconductor surface. The gate, 103, lies between spacers, 104, and source and drain regions, 105. The gate, 103, typically features an electrode formed from polysilicon. As shown in FIG. 1B, a silicide structures are typically formed by sputtering titanium (Ti), 106, over the entire semiconductor surface in a physical vapor deposition ("PVD") process. The resulting structure is then heated in a first rapid thermal anneal ("RTA1") process. As shown in FIG. 1C, this causes the titanium to react with the polysilicon in gate region, 103g, and also with the silicon of the source and drain regions, 105d. However, titanium deposited in the spacer and field oxide regions, u, does not react to form silicide. Moreover, the reaction between titanium and silicon in the source, 105d, drain, 105d, and gate, 103g, regions is "incomplete". The unreacted titanium, u, is selectively etched from the surface leaving only the "incompletely" reacted titanium silicide in regions, 103g and 105d. The "incompletely" reacted titanium silicide (TiSi.sub.2) has a crystallographic structure, known as C49. C49 TiSi.sub.2 is an unsatisfactory end product which has high sheet resistance. Titanium silicide requires further processing to obtain the necessary sheet resistance. A second RTA ("RTA2") is performed causing TiSi.sub.2 to change phase, forming a low resistance TiSi.sub.2, known as C54. C54 TiSi.sub.2 has a much lower sheet resistance than C49 and is used as an effective gate contact material.
C54 TiSi.sub.2 has many excellent properties, low junction leakage, low sheet resistance, low contact resistance, etc. However, it has been discovered as feature size and linewidth decrease, titanium silicide becomes a less than satisfactory silicide material. It has been observed that titanium silicide suffers from a linewidth dependent increase in sheet resistance. FIG. 2 shows the relationship between linewidth and sheet resistance of TiSi.sub.2 and CoSi.sub.2. As shown in FIG. 2, as linewidth decreases, the sheet resistance of titanium silicide increases. FIG. 2 shows that as TiSi.sub.2 linewidth decreases below 0.17 .mu.m, the sheet resistance of TiSi.sub.2 radically increases making it a wholly unsuitable material for the newer generation of microprocessors and memory chips.
Various attempts have been made to extend the life of TiSi.sub.2 as a useful process material. This has led to some useful improvements, but due to TiSi.sub.2 's grain structure, these improvements appear to be at an end. The chief limitation on TiSi.sub.2 is the number of nucleation sites. As linewidth decreases, the number of C54 nucleation sites also decreases leading to difficulties in forming low resistance C54 phase titanium silicide. This key factor has been very difficult to overcome in the present art.
Cobalt has been heralded as a promising possible successor material for titanium. The reason for this is shown in FIG. 2. CoSi.sub.2 does not suffer from the linewidth dependent sheet resistance problem. However, CoSi.sub.2 is not without its own unique problems. Unlike titanium, cobalt requires that the silicon deposition surfaces be cleaned (i.e., the native oxide layer etched off) prior to cobalt deposition. Furthermore, cobalt's suffers from extreme sensitivity to incorporation of surface and ambient contaminants during rapid thermal annealing (RTA) which makes a capping layer a virtual necessity. A process flow which addresses some of these problems is set forth in U.S. Pat. No. 5,047,367 by Wei, et al.
The invention of Wei describes a process for forming a titanium nitride/cobalt silicide bilayer for use in salicide technology and as contact via fills. Titanium is deposited on a silicon substrate then coated with a thin layer of Co. These layers are annealed in a nitrogen atmosphere. During anneal, cobalt migrates into the silicon substrate and titanium migrates upwards towards the surface. The surface titanium reacts with the atmosphere to form titanium nitride which protects the underlying cobalt layer. The cobalt then reacts with the silicon layer to form cobalt silicide. This method has the advantage of being a simple process which does not require the removal of the native SiO.sub.2 layer from the Si wafer surface. Additionally, the Ti layer getters the atmospheric and surface impurities from the Co layer preventing its contamination during processing. However, this process suffers from undesirable formation of a CoTi.sub.2 intermediate at the Ti/Co interface which inhibits CoSi.sub.2 formation.
Another present art process for fabricating a CoSi.sub.2 layer, involves the deposition of a titanium nitride (TiN) capping layer over a cobalt layer. This process begins with a silicon substrate having field oxide regions and spacers in place. The Si surface is stripped of its native oxide, then a layer of Co is formed over the surface. Subsequently, a capping layer of TiN is formed over the metallic cobalt. The substrate is then subject to rapid thermal annealing. This process avoids the formation of CoTi.sub.2 by using the TiN cap, which avoids the Ti/Co reaction during processing. However, this process suffers from incomplete reaction of the Co with Si. This incompleteness is more pronounced at narrow linewidths (e.g. less than 0.30 .mu.m) and at intermediate temperatures (e.g. temperatures in the range of 500-600 .degree. C.). The process also suffers from the effects of oxide outgassing which inhibits silicide formation by slowing Co diffusion.
Another method of forming CoSi.sub.2, is the direct formation of a Ti capping layer over the Co layer. Such a process is shown in U.S. Patent No. 5,780,362 by Wang and Maex. The Co layer is formed directly on the semiconductor substrate without stripping the native oxide. Subsequently, a Ti capping layer is formed over the Co layer. Since Ti is an excellent gettering material, the Ti capping layer removes impurities. The Ti layer removes impurities from the RTA ambient, as well as the SiO.sub.2 native oxide layer. This allows Co to react freely with the Si substrate. Unfortunately, this method has the same drawbacks as other methods where metallic Ti directly contacts Co, namely, Ti reacts with Co to form CoTi.sub.2. This consumes Co and hinders the formation of CoSi.sub.2.
What is needed is a method that eliminates the collective drawbacks of the existing techniques and allows the effective formation of a CoSi.sub.2 layer. The object of the present invention is to provide an efficient process for forming a CoSi, layer which does not incorporate impurities from the ambient or from surface outgassing. A further object of the present invention is to avoid the formation of undesirable intermediates, such as CoTi.sub.2, during processing. A further object of the present invention is to avoid process reactions which induce undue stresses in the substrate causing voiding of spacers.